As semiconductor technology has advanced, data processing applications, such as personal computers, workstations, communication systems, and the like have evolved rapidly to require faster and larger memory storage spaces. Specifically, semiconductor data processing systems typically implement RAM memories that allow any part of a memory to be read or written as fast as any part. Semiconductor RAMs are generally classified as non-volatile, static, and dynamic. Non-volatile RAMs are typically used for information that should be permanently stored, such as system information that is accessed during system start-up. A static RAM stores data in latches and is able to retain information while power is supplied to the memory. When the power is removed from the memory, the static memory loses all data stored therein. A dynamic random access memory (DRAM) is implemented through the use of a substantially smaller memory cell that must be refreshed periodically. Without such refresh operations, the DRAM cell would lose its information due to cell leakage through a capacitor implemented therein.
While DRAMs provide compact memory cells, the refresh requirements of DRAMs, in combination with other circuit requirements for proper operation, result in slower memory access times. Over the last two decades, the internal speed of data processors including microcontrollers and microprocessors has improved by a factor of approximately forty, while DRAM speed has improved by a factor of less than two. Furthermore, microprocessor clock frequencies are anticipated to quickly reach the 1 GHz range, while the fastest DRAM is only expected to reach 200 MHz in the same time period.
The speed of DRAMs is limited by several factors. For example, DRAMs tend to have longer cycle times because they are optimized for low power and not for speed, compared to static RAMs and some random logic circuits. Specifically, the speed with which a DRAM cell operates is limited by the requirement that the cell be periodically refreshed to compensate for the leakage of a capacitor used to implement each cell. In addition to the refreshing requirement, cycle times may also be adversely affected by contention from the refreshing requirement. Contention occurs when a DRAM memory cell that is being refreshed is concurrently required for access. In addition, read and write operations require a "pre-charge" or set up time, prior to "data sense and amplification.". Such information is well-known in the industry and is explained in greater detail in "Session XVII: Random Access Memories," by L. White, et al., published in the proceedings of the 1980 IEEE International Solid State Circuit Conference. Typically, the refresh operation has priority over other operations in DRAMs. Therefore, the read or write operation is postponed at least until the refresh operation is performed. In an effort to relieve such contention, some memory systems include cache memories, wherein a central processing unit of a data processing system is able to access a limited amount of memory more quickly and without potential contention problems, as such cache memory is typically implemented as a static RAM. However, even with the implementation of cache memories, cache misses occur when the required data is not available in the static RAM. Therefore, the data must then be accessed from the DRAM in a more time consuming operation.
In addition to the limitations associated with refresh operations and potential contention, DRAMs also have latency problems. Latency is a parameter used to measure an amount of time required to access a number of DRAM cells, a byte, or word after the appropriate address is asserted. Thus, the latency associated with a typical 16 megabit bank of DRAM cells that has 4,096 rows and 4,096 columns will be measured as a time required to step through such row or column of the memory, defined by the above-mentioned asserted address.
In an effort to solve some of the issues associated with refreshing, contention, and latency, several DRAM configuration and operation techniques have been implemented. Most recently, the use of a synchronous DRAM has been implemented to improve the speed associated with the conventional DRAM cell and memory peripheral circuits. Such synchronous DRAMs implement a 3-stage pipelined architecture to access conventional DRAM cells in a more timely manner. For additional information on such synchronous DRAM architectures, refer to "250MByte/Synchronous DRAM Using a 3-Stage Pipelined Architecture," IEEE Journal of Solid-State Circuits, Volume 29, No. 4, April 1994, by Yasuhiro Takai, et al., pp. 426-430. However, while methodologies, including synchronous DRAMs, have been implemented to optimize the latency, contention, and refresh requirements of DRAM cells, a requirement that a DRAM cell be refreshed still remains. This requirement imposes timing constraints that cannot be overcome using traditional memory cell implementations. Therefore, a need exists for a new memory cell, system architecture, and method for using both to meet the ever increasing demands for faster processing and greater memory capacity. Such implementation should be comprehensive and cost effective, as well as reduce the latency typically associated with the refresh requirements and resulting contention in a DRAM memory system.